Paper presentation, Monday, February 23, 5:30pm - 5:50pm Photoresist stabilization for double-patterning using 172-nm photoresist curing Paper 7273-12 Author(s): Thomas I. Wallow, Advanced Micro Devices, Inc. (United States); Junyan Dai, SOKUDO USA, LLC (United States); Charles R. Szmanda, Rohm and Haas Electronic Materials (United States); Nikolaos Bekiaris, Hiram Cervera, SOKUDO USA, LLC (United States); Ryoung-Han Kim, Jong-Wook Kye, Harry J. Levinson, Advanced Micro Devices, Inc. (United States); Glen Mori, SOKUDO USA, LLC (United States); Chi Truong, Rohm and Haas Electronic Materials (United States) In this paper, we present an update of the 2P1E double patterning process using flood exposure to 172 nm light to cure the first photoresist image. WE will discuss several advantages over purely chemical approaches. As an example of our results, Fig. 1 below shows two arrays of contact holes produced by the process outlined above. The SEM photographs show, respectively 70 nm (k1 = 0.337) and 65 nm (k1 = 0.313) contacts; both sets of which are below the practical single exposure contact limit. Some resists cure more effectively than others. This presents an opportunity to examine the chemical basis for the curing process. Accordingly, results from several resists will be shown and a mechanism will be proposed for the curing reaction. Poster presentations, Monday, February 23, 5:30pm - 8:00pm Track optimization and control for 32-nm node double patterning and beyond Paper 7272-128 Author(s): David Laidler, Philippe Foubert, Philippe J. Leray, Koen D'havé, IMEC (Belgium); Craig A. Rosslee, Len Tedeschi, Glen Mori, SOKUDO USA, LLC (United States) Given the stringent CD and defectivity requirements of the 32nm node and in particular those imposed by double patterning, optimization of the track process, control of that process and how to best utilize the track becomes ever more critical. In this paper we look at the different options available for optimizing track performance, with particular emphasis on CD control and defectivity. All experimental data presented in this paper was obtained on a state of the art ASML XT:1900Gi and Sokudo RF3S cluster at IMEC. Improved CD uniformity for shrink-assisted patterning Paper 7273-60 Author(s): Lu Chen, Nikolaos Bekiaris, Glen Mori, SOKUDO USA, LLC (United States) Chemical assisted feature shrink is used for small features like trenches in double patterning. For a typical process, the shrink rate is high and center-to-edge CD non-uniformity is commonly observed. As feature size goes to smaller scale, CDU control during the shrink process becomes increasingly important. Biased Hot Plate (BHP) has been used to improve DICD uniformity for conventional resist processes. By applying cross-wafer thermal bias to the shrink process, CD uniformity can be improved. Our experiments have demonstrated significant and consistent improvement of CD uniformity control using BHP. Post-develop blob defect reduction Paper 7273-71 Author(s): Masahiko Harumoto, Sei Negoro, Akihiro Hisai, Tanaka Michio, SOKUDO Co., Ltd. (Japan); Glen Mori, SOKUDO USA, LLC (United States); Mark Slezak, JSR Micro, Inc. (United States) This study reports on blob defect reduction and process impacts by Acid Rinse System. Blob defects that appear after develop are a common problem with i-line, KrF, ArF and ArF-immersion resists. Last year we reported Blob defects were influenced by the develop process and were able to be decreased by improving process. Furthermore we identified blob defects were caused from alkaline developer and could be reduced by neutralizing Acid Rinse. In this work, we designed a novel develop process and system that reduced blob defects. We evaluated this system on the non-topcoat immersion resist. The blob defects on immersion resist were also eliminated by this system but affected by each resist surface condition. We reports that Acid Rinse System significantly reduced blob defect counts, and whether influenced other process impacts. Finally we report the mechanism of the blob defects reduction. Analysis of the effect of point-of-use filtration on microbridging defectivity Paper 7273-75 Author(s): Jennifer Braggin, Entegris, Inc. (United States); Roel Gronheid, Shaunee Y. Cheng, Dieter Van Den Heuvel, Sophie Bernard, Philippe Foubert, IMEC (Belgium); Craig A. Rosslee, SOKUDO USA, LLC (United States) Microbridging defects have emerged as the top yield detractor in semiconductor manufacturing. It is generally recognized that there are multiple root causes for microbridging defectivity. Image and resist contrast and different developer techniques have been studied and their contribution to microbridging defectivity has been described. In this study we will focus on the effect of point-of-use filtration and how it is best used to mitigate microbridging defectivity. A design of experiment methodology will be utilized to understand the effect of various filter and filtration parameters on microbridging defectivity, including filter retention rating, filter media and design, filtration rate, and controlled filtration pressure. It is anticipated that by better understanding the effect of point-of-use filtration on microbridging defectivity, guidelines for better control of this type of defect may be formulated. Performance of an ArF siloxane BARC exposed to a 172-nm UV cure for double patterning applications Paper 7273-107 Author(s): Kyle Y. Flanigan, Joseph T. Kennedy, Benjamin Z. Y. Wu, Ron Katsanes, Honeywell Electronic Materials (United States); Thomas I. Wallow, Advanced Micro Devices, Inc. (United States); Junyan Dai, SOKUDO USA, LLC (United States); Nikolaos Bekiaris, Applied Materials, Inc. (United States); Hiram Cervera, Glen Mori, SOKUDO USA, LLC (United States) As IC manufactures explore different paths to meet the resolution requirements for next generation technology, patterning schemes utilizing double photoresist patterning (DP) processes are under extensive evaluation or in some cases may already be in use. One DP process being investigated uses a 172nm UV cure to render the first photoresist pattern immiscible to the casting solvent and developer solution used to define the second photoresist pattern. This work investigates the use of siloxane bottom antireflective coatings (SiBARC) for the patterning of the first photoresist features and whether the properties of the SiBARC film are altered by the UV cure. CD and defect improvement challenges for immersion processes Paper 7273-126 Author(s): Seiji Nakagawa, Toshiba Corp. (Japan); Timothy B. Michaelson, SOKUDO USA, LLC (United States); Seiji Shitani, Toshinari Yamasaki, Keisuke Ehara, Toshiba Corp. (Japan); Akihiko Morita, Jeonghun Kim, Masashi Kanaoka, Shuichi Yasuda, Masaya Asai, SOKUDO Co., Ltd. (Japan) Immersion lithography presents unique challenges, including stringent requirements in the areas of CD control and defectivity. The 2007 ITRS roadmap, for 3x nm Flash and MPU 1/2 pitch processes, predicts the defect density and CD control in patterned resist should be less than 0.02 defects/cm2 and 1.3nm (3 sigma). The requirements for double patterning processes will more difficult, for example, less than 0.01 defects/cm2 and 0.65nm (3 sigma). The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve world class CD and defectivity performance in a state of the art manufacturing facility. Backside EBR process performance with various wafer properties Paper 7273-135 Author(s): Tomohiro Goto, Kazuhito Shigemori, Masakazu Sanada, SOKUDO Co., Ltd. (Japan) We focus on the wafer bevel properties such as bevel shape and surface condition that would be affected on the back side EBR coating process performance in photo process. Based on experimental results, we will discuss what wafer properties will be important to control film edge exclusion to prevent yield loss. Defectivity process optimization on immersion topcoat less resist stacks Paper 7273-138 Author(s): Len Tedeschi, SOKUDO USA, LLC (United States); Kazuhito Shigemori, Akihiro Hisai, Masahiko Harumoto, SOKUDO Co., Ltd. (Japan); Suping Wang, Coen Verspaget, Orhangazi Tanriseven, Raymond Maas, Joerg Mallmann, ASML Netherlands B.V. (Netherlands) Demand for Immersion topcoat-less (TC-less) resist processes is being driven by the desire to reduce the cost per wafer pass. Two key characteristics, required by high speed immersion scanners, of TC-less resist are high receding contact angle and low leaching rates. The extremely hydrophobic surface required by the scanner provides significant challenges to the remaining processing steps, especially (developer) process related defects: pattern collapse and hydrophobic residuals. Recent developments in materials and processing techniques have led to very promising results. In this paper the following will be presented: Defectivity results on 45nm L/S of several TC-less resists, including the effects of optimized track rinse recipes. Results of a fundamental study on static contact angles changes of different TC-less resists after each track process step to identify where in the process issues originate. Imaging and defectivity results of 38nm L/S using the TC-less champion process are presented. These results illustrate the capability of the ASML TWINSCAN XT:1900i / Sokudo RF3i litho cluster of printing 38 nm L/S in a single exposure.