SPIE Advanced Lithography 2008 Technical Conference SOKUDO Co., Ltd. introduces 1 oral presentation and 5 posters at the Conference. Immersion lithography bevel solutions (Oral Presentation) Paper 6922-158 Author(s): Len Tedeschi, SOKUDO Co., Ltd. (USA); Osamu Tamada, Masakazu Sanada, Shuichi Yasuda, Masaya Asai, SOKUDO Co., Ltd. (Japan) Date: Monday, 25 February 2008 The introduction of Immersion lithography, combined with the desire to maximize the number of potential yielding devices per wafer, has brought wafer edge engineering to the forefront for advanced semiconductor manufactures. Bevel cleanliness, the position accuracy of the lithography films, and quality of the EBR cut has become more critical. In this paper, the effectiveness of wafer track based solutions to enable state-of –art bevel schemes is explored. This includes an integrated bevel cleaner and new bevel rinse nozzles. The bevel rinse nozzles are used in the coating process to ensure a precise, clean film edge on or near the bevel. The bevel cleaner is used immediately before the wafer is loaded into the scanner after the coating process. The bevel cleaner shows promise in driving down overall defectivity levels, while not damaging films on the bevel. Film stacking architecture for immersion lithography process (Poster) Paper 6922-109 Author(s): Tomohiro Goto, Masakazu Sanada, Tadashi Miyagi, Kazuhito Shigemori, Masashi Kanaoka, Shuichi Yasuda, Osamu Tamada, Masaya Asai, SOKUDO Co., Ltd. (Japan) Date: Monday, 25 February 2008 We report on effective film stacking architecture with maximum lithographic area. The back side approach was used for all layers in the stack (BARC, resist and TC). The back side coating process was constructed based on Design of Experiments. It was found that edge exclusion width was controlled on the bevel/edge with some specific factors of the back side EBR coating process. Defectivity performance was also studied and results showed acceptable stack architecture with no specific defects on the wafer. The defectivity performance of the back side EBR process is discussed as well as that of the top side EBR process. Based on these experimental results, we will propose the mechanism of specific defects by the particles generated from peeling. Post develop stain defect reduction (Poster) Paper 6923-139 Author(s): Masahiko Harumoto, Akihiro Hisai, Minoru Sugiyama, Takuya Kuroda, SOKUDO Co., Ltd. (Japan) Date: Monday, 25 February 2008 This study reports on stain defect reduction on KrF, ArF and Immersion resist systems. Stain defects that appear after develop are a common problem with i-line, KrF, ArF and ArF-immersion resists. Last year we reported a reduction of this type of defect by optimizing the developer process. However, that optimized process used a long rinse time, and this negatively impacts throughput. In this work, we designed a novel develop process that reduced stain defects on the resist. Previous work showed that stain defect formation was mainly governed by the develop process conditions. Hence, in this work we focused on develop process improvements. We identified a rinse process that both significantly reduced stain defect count and used a shorter rinse process time. In addition to reducing defect count, we identified the defect reduction mechanism. Wafer shape measurement and compensation at the track PEB for improved CD uniformity (Poster) Paper 6923-143 Author(s): Junyan Dai, Lu Chen, Timothy B. Michaelson, Hiram Cevera, Brian C. Lue, Harald Herchen, Kim R. Vellore, Nikos Bekiaris, SOKUDO USA, LLC Date: Monday, 25 February 2008 As the industry scales to smaller features sizes, the control of the critical dimension uniformity (CDU) becomes increasingly important. The measured CD variation (prior to etch) may come from many sources such as the scanner, track, and metrology. Several methodologies have been developed to improve CDU such as local dose correction and multi-zone post exposure bake (PEB) plates. Some have proposed biasing multi-zone bakes from the center to edge, but this generally requires knowledge of the shapes of incoming wafers. The actual production wafers shape will vary from process flow to process flow (and even within a process flow). Adding an extra measurement step will dramatically lower the productivity. To address the effect of the variation of incoming wafer shape during PEB, we have implemented two different wafer shape compensation methods into our PEB design. Our preliminary results demonstrate significant CDU improvement for bowed wafers. Demonstration of production readiness of an immersion lithography cell (Poster) Paper 6924-190 Author(s): Paolo Piacentini, STMicroelectronics (Italy) Date: Thursday, 28 February 2008 This paper presents the results of the evaluation and qualification of the Sokudo RF3i track on immersion process. This was the first track of this kind installed in a lithography production operation, and it was interfaced with a 1.2NA immersion scanner. The overall process was qualified through the full range of lithographic parameters, including in particular, defectivity. All immersion-related modules were tested and optimized, and the system was introduced to advanced prototypes (45nm node). A lithographic and process assessment of photoresist stabilization for double-patterning using 172-nm photoresist curing (Poster) Paper 6923-79 Author(s):  Nikolaos Bekiaris, Hiram Cervera, Junyan Dai, SOKUDO Co., Ltd.; Ryoung-Han Kim, Alden Acheta, Thomas Wallow, Jong-Wook Kye, Harry J. Levinson, Advanced Micro Devices, Inc.; Thomas Nowak, James Yu, Applied Materials, Inc. Date: Monday, 25 February 2008 Double-patterning methods that simplify integration of lithographic and etch processes are of growing interest due to their potential for improved manufacturing throughput and cost savings.  A substantial body of work in this area has centered on processes that maintain two lithographic steps, but transfer the resulting pattern in a single etch step.  Enabling photoresist technologies for implementing such double-exposure, single-etch approaches center on stabilizing a first photoresist pattern to the processing steps required for generating the second pattern.  Numerous chemical, photochemical, and electron- or ion-beam curing methods have been explored.  However, detailed studies of advantages and limitations of these methods are only beginning to emerge.  In this presentation, we assess photoresist stabilization using 172nm UV cure.